* (C) Copyright Efficient Power Conversion Corporation. All rights reserved.
*****************************************************************************
* Version History:
* 1.00: 08/13/2020 - Initial Model Creation
* 1.01: 04/04/2024 - Adapted for Simplis

.subckt EPC2207 gatein drainin sourcein
*#ASSOC Category=NMOS Symbol=nmos_sub mapping=2,1,3


.param  aWg={Wg*1E-3} Wg=362000 A1={3.625e-02*aWg} k2=1.874e+00 k3=9.000e-02 rpara=1.243e-02
.param  si={aWg*1.200e-03} so={aWg*6.150e-03} sr={aWg}
+	rpara_s_factor=2.406e-01 aITc=3.000e-03 arTc=-6.700e-03 k2Tc=6.000e-04
+	x0_0=4.938e+00 x0_0_TC=-2.000e-03 x0_1=-1.285e-01 x0_1_TC=0.000e+00
+	dgs1=4.3e-07 dgs2=2.6e-13 dgs3=0.8 dgs4=0.23
+	ags1={1.045e-09*si} ags2={8.283e-10*si} ags3=1.376e+00 ags4=1.808e-01
+	ags5={0.000e+00*si} ags6=7.480e+01 ags7=1.055e+01
+	agd1={1.124e-15*sr} agd2={1.409e-13*sr} agd3=-6.900e+00 agd4=5.314e+00
+	agd5={2.769e-14*sr} agd6=-2.326e+01 agd7=2.129e+01 agd8={1.081e-15*sr}
+	agd9=-4.326e+01 agd10=1.029e+01
+	asd1={5.053e-11*so} asd2={3.977e-11*so} asd3=-1.941e+01 asd4=2.356e+00
+	asd5={1.449e-11*so} asd6=-8.476e+01 asd7=1.007e+01 asd8={8.934e-11*so}
+	asd9=-3.023e+01 asd10=2.523e+01
+	rg_value=0.3

.model rpar res(TC1={-1.0*arTc} T_measured=25)
rd drainin  drain  rpar {(1-rpara_s_factor)*rpara}
rs sourcein source rpar {rpara_s_factor*rpara}
rg gatein gate {(rg_value)}

*Large resistors to aid convergence
Rcsdconv drain source {100000Meg/aWg}
Rcgsconv gate source {100000Meg/aWg}
Rcgdconv gate drain {100000Meg/aWg}

gswitch drain source Value {if(v(drain,source)>0,
+	(A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,source)-(k2*(1-k2Tc*(Temp-25))))/k3))* 
+	v(drain,source)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,source))*v(drain,source)) ),
+	(-A1*(1-aITc*(Temp-25))*log(1.0+exp((v(gate,drain)-(k2*(1-k2Tc*(Temp-25))))/k3))* 
+	v(source,drain)/(1 + (x0_0*(1-x0_0_TC*(Temp-25))+x0_1*(1-x0_1_TC*(Temp-25))*v(gate,drain))*v(source,drain)) ) )}

ggsdiode gate source VALUE {if( v(gate,source) < 10,
+	0.125*aWg/1077*(dgs1*(exp((v(gate,source))/dgs3)-1)+dgs2*(exp((v(gate,source))/dgs4)-1)),
+	0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }

ggddiode gate drain Value {if( v(gate,drain) < 10,
+	0.125*aWg/1077*(dgs1*(exp((v(gate,drain))/dgs3)-1)+dgs2*(exp((v(gate,drain))/dgs4)-1)),
+	0.125*aWg/1077*(dgs1*(exp((10)/dgs3)-1)+dgs2*(exp((10)/dgs4)-1)) ) }

*Gate-source capacitance
C_GS        gate source  {ags1}  TC=0,0
gC_CGS1     gate source Q={(0.5*ags2*ags4*log(1+exp((v(gate,source)-ags3)/ags4))+
+           ags5*ags7*log(1+exp((v(source,drain)-ags6)/ags7)) )}

*Gate-drain capacitance
C_GD        gate drain  {agd1}  TC=0,0
gC_CGD1     gate drain Q={(0.5*ags2*ags4*log(1+exp((v(gate,drain)-ags3)/ags4))+
+           agd2*agd4*log(1+exp((v(gate,drain)-agd3)/agd4))+
+           agd5*agd7*log(1+exp((v(gate,drain)-agd6)/agd7))+
+           agd8*agd10*log(1+exp((v(gate,drain)-agd9)/agd10)))}

*Source-drain capacitance
C_SD        source drain  {asd1}  TC=0,0
gC_CSD1     source drain Q={(asd2*asd4*log(1+exp((v(source,drain)-asd3)/asd4))+
+           asd5*asd7*log(1+exp((v(source,drain)-asd6)/asd7))+
+           asd8*asd10*log(1+exp((v(source,drain)-asd9)/asd10)) )}

.ends